Each generation of memory interface products is designed to handle faster data rates and more and more complicated applications. In terms of receiver design, the signal integrity design is much more challenging than for previous memory generations. The receiver has to tolerate different channel losses and reflections for all applications. For example, the data rate has a large range from 3.2 Gps to 4.6 Gps. Different manufacturers might each have different customized signal path designs. The receiver has to support both 1 dpc (DIMMs per channel) and 2 dpc applications.
It would be desirable to implement a wide programmable gain receiver data path for single-ended memory interface application.